In the designing of a digital computer, a designer will determine the speed of operation of the computer (i.e. the cycle time). This determination of the cycle time is typically based on the speed of the adder that is used in the computer. Therefore, to satisfy the demand for higher speed (i.e. lower cycle time) computers, faster adders need to be provided.
The usual design of an adder, such as a 32-bit adder, is an adder that is partitioned into many smaller adders with carry-look-ahead logic. The lowest order adder will perform addition on, for example, the eight lowest order bits, the second lowest order adder will perform addition on the eight next lowest order bits, etc. Carry-look-ahead logic is used to generate carries from lower-order adder into the next higher-order adders. For example, the carry from the addition of the eight lowest order bits &lt;7:0&gt; of the two numbers will be generated by the carry-look-ahead logic and provided to the next highest-order adder. The next highest order adder will then perform addition on bits &lt;15:8&gt;, adding in the carry from the carry-look-ahead logic.
When a relatively large adder is used, such as a 32-bit adder, there are problems associated with the carry-look-ahead method. One problem is that the "critical timing path" is through the carry-look-ahead logic so that the adder is limited by how fast a carry can be generated in a lowest-order bit and propagated through the carry-look-ahead logic to the highest-order bit for which there can be a carry. As an example, if four 8-bit adders are used to make up a 32-bit adder, a carry that is generated in the first lowest-order bit can be propagated up to the 24th bit. This carry from the 24th bit will be provided to the highest-order 8-bit adder, which will operate on bits &lt;31:24&gt;. The propagation of a carry through 24 bits takes a relatively long time and requires a relatively cumbersome design.
The logic used in the carry-look-ahead logic is known as propagate and generate logic. In the example of a 32-bit adder, the carry for the 24th bit will be determined by seven terms, using this generate and propagate logic. (This will be described in more detail later). The use of seven terms to determine a carry bit necessitates the use of relatively large gates (e.g. gates with seven inputs). The larger gates are slower than smaller gates, and may not even be allowed by the manufacturing technology. Furthermore, the wire delay with the use of standard carry-look-ahead logic is relatively long, since the logic has to span the full width of the adder.
There is a need for a high-performance adder that has improved speed, without using carry-look-ahead logic such as that which has generally been used.